Changelog
=========

v0.1.2
-------

* R_MAX_VULQANO now is an environment variable with default value 16.

v0.1.1
-------

* Bugfix pypi upload

v0.1.0
-------

* Update documentation
* Rename package
* Update qtealeaves compatibility to version to 1.1.8

v0.0.24
-------

* Added code to test the circuit before and after the optimization, taking
  into account all form of noise

v0.0.23
-------

* Bugfix: now a creshed simulation can be restored multiple times

v0.0.22
-------

* Implement restore python tn simulation

v0.0.21
-------

* Bugfix in restoring simulations from mps
* Bugfix in Postprocessing simulation with skipped steps

v0.0.20
-------

* Update to latest qtealeaves version
* Now `MPS` simulations are possible

v0.0.19
-------

* Implemented lock fictitiuous gate for blocking a lattice site (useful for circuits with large idle regions).

v0.0.18
-------

* Bugfix: add has_obc=False when creating block terms in quantumsymulation.
* Improvements: collapsed quantum simulation enabled.
* Improvements: reflection symmetry for collapsed quantum simulation enabled.
* Improvements: custom rules sets enabled.
* Minor improvements and bugfixes.

v0.0.17
-------

* Bugfix: added missing tools folder in the git repository.
* Improvements: quantum_dynamics parametes and output improved.


v0.0.16
-------

* Bugfix: added missing compiler unit test in the git repository.

v0.0.15
-------

* Bugfix in error evaluation.


v0.0.14
-------

* Simulated annealing for cricuits acting on 2d qubits lattices implemented.


v0.0.13
-------

* Simulated annealing with parametric gates implemented.


v0.0.12
-------

* Now the user can list the classes of transition rules that they wants to involve in the dynamics.


v0.0.11
-------

* Project structure redesigned.
* SA optimization of quantum circuits with discrete gates and 1d connectivity is fully implemented and tested.
* QA optimization of quantum circuits with discrete gates and 1d connectivity is implemented but not fully tested.
* SA optimization of quantum circuits with continuous gates and 1d connectivity is not yet implemented.